Silicon Engineering & Verification

Working on hardware verification, FPGA Development, ML acceleration, PCB Design & more.

M.S. in Electrical and Computer Engineering from UC Davis. Specializing in Design Verification, FPGA development and Hardware acceleration. I love building and verifying digital hardware systems.

Technical Skills

Hardware Stack
RISC-VARM CortexXilinx Zynq SoCIntel DE10 SoCSTM32
HDL & Verification
VerilogSystemVerilogVHDLUVMPyUVM
Software & Scripts
C/C++Vivado HLSPythonMATLABTCL
Contact Me GitHub LinkedIn

Silicon Verification & Deployment

HFT Microarchitecture // SystemVerilog & Python

NASDAQ ITCH 5.0 Hardware Decoder

Engineered a 3-stage byte-serial pipelined NASDAQ ITCH 5.0 hardware decoder in SystemVerilog for high-frequency trading (HFT) applications, streaming market protocol data at a deterministic 1 byte/cycle while eliminating variable-length message alignment overhead. Designed a low-area microarchitecture on a Xilinx Zynq-7020 FPGA by deploying a 3-state length-prediction FSM and a 2-state Mealy FSM parser that multiplexes 8 per-type decoders over a shared broadcast data bus using one-hot valid signaling. Constructed an end-to-end integration testbench and a Python golden reference model validated against 100k real BX messages.

SystemVerilogPythonFPGAHFT
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Verification Framework // SystemVerilog & UVM

RISC-V UVM Verification Ecosystem

Designed a modular UVM ecosystem for a 32-bit RV32I core enabling directed and constrained-random verification. Developed a Register Abstraction Layer (RAL) with front-door/back-door access and integrated TLM-based transaction flows. Debugged corner-case failures to achieve >98% functional coverage across all instruction groups, increasing test regression throughput by 30%.

SystemVerilogUVMRAL Verification
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Hardware Acceleration // SystemVerilog & Python

Hardware-Accelerated Network Inspector

Designed a 3 stage SystemVerilog pipeline inspecting Ethernet, IPv4, TCP, and UDP at 1 Gbps line rate with an 8 entry programmable rule table and 3 hardware anomaly detectors, packaged as a reusable AXI Stream IP at 125 MHz on a Xilinx Zynq SoC. Built self checking SystemVerilog testbenches for each pipeline stage and the full design, verifying bit accurate rule matching and anomaly detection across targeted stimulus. Validated on PYNQ Z2 hardware via a PYNQ Python driver and AXI DMA, classifying 703 live packets in real time, dropping 492 by rule and flagging 158 anomalies.

SystemVerilogAXI-StreamNetwork SecurityZynq SoC
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[ DRAG ME ]

Miscellaneous Systems Projects

EDA Algorithms // Python & OpenCV

ML-Based PCB Auto-Routing Pipeline

Implemented and validated an ML-guided PCB auto-routing pipeline utilizing a U-Net segmentation model backed by an integrated A* search algorithm. Adjusted routing parameters across multiple test layouts to perform batch inference testing, resulting in a 5% optimization improvement in baseline trace lengths and total via counts.

PythonOpenCVU-NetA* Routing
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[ DRAG ME ]
Core Registry

RTL, Design Verification & FPGA Subsystems

HFT Microarchitecture // SystemVerilog & Python

NASDAQ ITCH 5.0 Hardware Decoder

Engineered a 3-stage byte-serial pipelined NASDAQ ITCH 5.0 hardware decoder in SystemVerilog for high-frequency trading (HFT) applications, streaming market protocol data at a deterministic 1 byte/cycle while eliminating variable-length message alignment overhead. Designed a low-area microarchitecture on a Xilinx Zynq-7020 FPGA by deploying a 3-state length-prediction FSM and a 2-state Mealy FSM parser that multiplexes 8 per-type decoders over a shared broadcast data bus using one-hot valid signaling. Constructed an end-to-end integration testbench and a Python golden reference model validated against 100k real BX messages.

SystemVerilogPythonFPGAHFT
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Verification Framework // SystemVerilog & UVM

RISC-V UVM Verification Ecosystem

Designed a modular UVM ecosystem for a 32-bit RV32I core enabling directed and constrained-random verification. Developed a Register Abstraction Layer (RAL) with front-door/back-door access and integrated TLM-based transaction flows. Debugged corner-case failures to achieve >98% functional coverage across all instruction groups, increasing test regression throughput by 30%.

SystemVerilogUVMRAL Verification
View Source →
Hardware Acceleration // SystemVerilog & Python

Hardware-Accelerated Network Inspector

Designed a 3 stage SystemVerilog pipeline inspecting Ethernet, IPv4, TCP, and UDP at 1 Gbps line rate with an 8 entry programmable rule table and 3 hardware anomaly detectors, packaged as a reusable AXI Stream IP at 125 MHz on a Xilinx Zynq SoC. Built self checking SystemVerilog testbenches for each pipeline stage and the full design, verifying bit accurate rule matching and anomaly detection across targeted stimulus. Validated on PYNQ Z2 hardware via a PYNQ Python driver and AXI DMA, classifying 703 live packets in real time, dropping 492 by rule and flagging 158 anomalies.

SystemVerilogAXI-StreamNetwork SecurityZynq SoC
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RTL Design & Integration // Verilog

32-Bit Pipelined RISC-V Processor on FPGA

Designed and implemented a 32-bit RISC-V processor in Verilog on the Intel DE10-Lite FPGA with a single-issue, in-order 4-stage pipeline. Engineered control-flow recovery and hazard mitigation via a decode-stage branch/jump ALU (1-cycle penalty) and merged MEM+WB forwarding. Integrated a memory-mapped Avalon-MM SoC containing dual-port SRAM, UART, and GPIO peripherals.

Verilog RTLComputer ArchitectureAvalon-MM
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Hardware Acceleration // Vivado HLS

Accelerated Quantized Neural Network (MNIST)

Implemented a quantized neural network for MNIST classification on the PYNQ-Z2 board. Designed modular processing layers in C++ (HLS) and integrated them via AXI-Stream for end-to-end hardware acceleration on the Zynq-7000 SoC. Optimized pipeline latency and FPGA fabric resource usage, achieving ~10x performance improvements for real-time classification.

Vivado HLSAXI-StreamZynq SoC
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DSP Hardware Acceleration // Python & PYNQ

DMA-Driven FIR Accelerator on Zynq SoC

Designed and implemented a streaming FIR filter accelerator on the Zynq-7000 programmable logic utilizing an AXI-DMA block. Orchestrated data transfers and performance benchmarking via the Python-based PYNQ framework, achieving a 4.77x end-to-end execution speedup over Arm Cortex-A9 software processing for large streaming workloads.

Zynq-7000AXI-DMAPYNQDigital Signal Processing
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Extended Registry

Miscellaneous Engineering Projects

EDA Algorithms // Python & OpenCV

ML-Based PCB Auto-Routing Pipeline

Implemented and validated an ML-guided PCB auto-routing pipeline utilizing a U-Net segmentation model backed by an integrated A* search algorithm. Adjusted routing parameters across multiple test layouts to perform batch inference testing, resulting in a 5% optimization improvement in baseline trace lengths and total via counts.

PythonOpenCVU-NetA* Routing
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Physical Systems Integration // PCB Design

4-Layer ESP32 System Design & Testing

Designed and assembled a 4-layer ESP32-based functional PCB integrated with onboard sensor data streams. Handled physical hardware bring-up procedures, tracking pathing checkouts, power-on sequencing, and bus signaling communications using oscilloscopes and logic analyzers.

4-Layer PCBSignal IntegrityOscilloscope Verification
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